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Application 1. 2D SC enabled emitter integrated on Si photonic chip.

Task 3.1. Design of the Si photonic components and photonic simulations. (M01-M24) [MELLANOX, BIU]

This Task will focus on the design and simulation of the SiPh adiabatic coupling structures that will enable the efficient light coupling between the 2D diode structure and the nano-photonic circuitry. Two design iterations are foreseen: the first round will provide quick feedback on the actual performance of the designed components, assisting the proper adjustment of the design and simulation parameters to the foundry capabilities (MS5). The second will leverage the available characterization data to optimize the performance of the adiabatic coupling structures, enhancing the overall performance of the emitter (MS7). The adiabatic coupling simulations will rely on a commercially available EigenMode Expansion software (MODE Solutions – Lumerical), whereas the chip layout, to be submitted to the foundry, will be generated using PhoenixBV Optodesigner.


Task 3.2. Fabrication of the Si photonic platform. (M09-M30) [BIU, MELLANOX]

T3.2 is dedicated on the fabrication processes of the Si photonic platform which will enable the development of the three different types of emitters: i) LEDs on VTD, ii) DJT configurations and iii) DJT laser. Clean room fabrication (BIU) includes the assembly of contact pads and passivation of devices to construct the diode devices on bare Si. The emission spectra will validate the work conditions towards integration with SiPh waveguide.



Task 3.3. Fabrication of the 2D-enabled emitters by LDT (M13-M36) [SOUTHAMPTON, NTUA, BIU]

In this Task, the LDT method will be applied for the fabrication of VTD and DJT structures on the Si photonic transceiver developed in Task 3.2. The VTD configuration will be constructed from oppositely biased graphene layers spaced from the emitting semiconductor by thin layers of h-BN. This will be achieved by implementing the optimized LIBT process (T2.2, 2.3) in distinct steps for the transfer of single layers of Graphene and h-BN layers consecutively (MS6). For the fabrication of the direct junction (DJT), the LIBT technique will be employed, using 1500 nm laser light. This wavelength will be transmitted through the silicon receiver, whilst being absorbed at the donor/carrier interface.



Task 3.4. Morphological, electro-optical characterization of the 2D-enabled emitters (M13-M36) [BIU, NTUA]

NTUA will conduct full structural and morphological characterization by SEM, AFM. Electrical characterization performed by BIU, will resolve built-in potential and carrier type, concentration, photoconductivity spectroscopy. All emitter test structures will be optically characterized by BIU with transmission, reflection, photoluminescence and electroluminescence spectroscopies. Following the successful finalization of each fabrication round, the realized SiPh structures will be sent to MELLANOX for detailed performance characterization (D3.1, MS8). To this end, a customized probe station will be employed capable of both in-plane and out-of-plane light coupling.



Task 3.5. Integration and system-level evaluation and testing of Si photonic chip. (M13-M36) [MELLANOX]

Test runs will be carried out regularly with different design variations. The emitter test structures will be characterized by MELLANOX in terms of key optical and environmental characteristics. The final emitter devices will be integrated in transceiver prototypes (evaluation boards) targeting different application domains: i) LiFi transceiver for IoT (D3.2); ii) silicon photonic transceiver for datacenter interconnects (D3.3); and iii) flexible transceiver platform for video broadcast in consumer electronics and personal area networks (D3.4). The transceiver prototypes will be tested as standalone devices as well as in combination with MELL commercial systems (e.g. network processors, NICs).

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